![]() ![]() Likewise, the simple decoders are limited to instructions that can be translated into one micro-op. Thus, x86 instructions that operate on the memory (e.g., add this register to this location in the memory) can only be processed by the general decoder, as this operation requires a minimum of three micro-ops. The general decoder can generate up to four micro-ops per cycle, whereas the simple decoders can generate one micro-op each per cycle. The micro-ops are reduced instruction set computer (RISC)-like that is, they encode an operation, two sources, and a destination. x86 instructions are decoded into 118-bit micro-operations (micro-ops). This restricts the Pentium Pro's ability to decode multiple instructions simultaneously, limiting superscalar execution. ![]() The decoders are unequal in ability: only one can decode any x86 instruction, while the other two can only decode simple x86 instructions. The Pentium Pro has an 8 KB instruction cache, from which up to 16 bytes are fetched on each cycle and sent to the instruction decoders. It also had a wider 36-bit address bus, usable by Physical Address Extension (PAE), allowing it to access up to 64 GB of memory. The Pentium Pro thus featured out of order execution, including speculative execution via register renaming. The Pentium Pro pipeline had extra decode stages to dynamically translate IA-32 instructions into buffered micro-operation sequences which could then be analysed, reordered, and renamed in order to detect parallelizable operations that may be issued to more than one execution unit at once. ![]() The Pentium Pro ( P6) implemented many radical architectural differences mirroring other contemporary x86 designs such as the NexGen Nx586 and Cyrix 6x86. It has a decoupled, 14-stage superpipelined architecture which used an instruction pool. ![]() The Pentium Pro incorporated a new microarchitecture, different from the Pentium's P5 microarchitecture. The lead architect of Pentium Pro was Fred Pollack who was specialized in superscalarity and had also worked as the lead engineer of the Intel iAPX 432. ![]()
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